1. Field of the Invention
This invention relates to a clock signal selection circuit.
2. Description of the Prior Art
A clock signal selection circuit for selecting one of first and second clock signals. FIG. 5 is a logic circuit diagram of a first prior art clock signal switching circuit. FIG. 6 shows waveforms of outputs at respective portions of the first prior art clock signal switching circuit.
The first prior art clock signal switching circuit shown in FIG. 5 comprises a first gate G11 for effecting operation of AND between a control signal and a first clock signal CLK1, a second gate G12 for effecting operation of AND between a control signal and a second clock signal CLK2, and an OR gate G13 for effecting operation of OR between outputs of the first and second gates G11 and G12.
As shown in FIG. 6, the first prior art clock signal selection circuit changes the outputting of the first clock signal CLK1 from that of the second clock signal CLK2 in response to the control signal CONT to produce a selected clock signal CLK13.
FIG. 7 is a logic circuit diagram of a second prior art clock signal selection circuit. The second prior art clock signal selection circuit comprises first and second D type flip-flops F1 and F2, first, second, and third gates G14, G15, G16, first and second delay circuits DY1 and DY2 and an inverter IV1. FIG. 8 is a time chart showing respective outputs of the second prior art clock signal selection circuit. As shown in FIG. 8, when the control signal CONT is H, an output Q2 of the second flip-flop F2 is logic H, so that the second clock signal CLK2 is selected. This causes an output Q1 of the first flip-flop F1 to be L, so that outputting of the first clock signal CLK1 is inhibited. When the control signal goes to L, the output Q2 of the flip-flop F2 goes to logic L and the output Q1 of the flip-flop F1 goes to H, so that outputting of the second clock signal CLK2 is inhibited and that of the first clock signal CLK1 is permitted.
FIG. 9 is a logic circuit diagram of a third prior art clock signal selection circuit. The third prior art clock signal selection circuit has fourth and fifth gates G17 and G18 in addition to a structure of the second prior art wherein the D type flip-flops F1 and F2 with the reset inputs are replaced with D type flip-flop F3 and F4 having no reset input.
In the first prior art clock signal selection circuit, there is a problem that it generates a short obstructive pulse Px during switching operation as shown in FIG. 8. In the second and third prior art clock signal selection circuits, delay circuits DY1 and DY2 are used to prevent hazard. However, there is a problem that hazard is not prevented sufficiently because there is two portions which judge the logic level of the control signal, so that there is a possibility that the first flip-flop and the second flip-flop F1 and F2 output different results due to time delay. Moreover, in the second and third prior arts, there is a further problem that in the manufacturing of integrated circuit including this clock signal selection circuit is difficult because there is analog type delay circuits DY1 and DY2 whose delay time should be controlled in the manufacturing processing.